Exploiting the Limits of Scaling and Beyond

Luc Van den hove
President & CE
imec

The research and subsequent introduction of high-k/metal gate in chip fabrication a few years ago was a major change for the semiconductor R&D. It opened the pathway to exploring the characteristics of many other materials to see how we could use them to our advantage. The main reason for doing so, was that we had come to the end of the era of the so-called ‘easy scaling’. This was the era where scaling all parameters and making devices ever smaller automatically led to an improved performance.

The importance of new materials will only grow in the near future.  Next on the agenda are high-mobility materials, such as germanium and III/V materials. Further out some more novel materials are appearing, and researchers are already looking at how electronics can be made with 2D materials such as graphene or molybdenum disulfide.

Next to material innovation also new transistor structures are needed. The recently introduced FinFET architecture provides a better electrostatic control of the transistor channel. Exploring this idea further, nanowire transistors where the channel is completely wrapped by the gate is foreseen. The use of vertical nanowires could provide some interesting advantages. Currently, the investigation of such very small nanowires using high-mobility materials is high on R&D agendas. Next to this, steep subthreshold devices such as TunnelFETs are also being explored since they allow a further reduction of the supply voltage and power consumption.

We’re on the brink of a paradigm shift. Some of the imminent breakthroughs may well have an impact comparable to the invention of the transistor more than 65 years ago.